A 12×10 Gb/s fully integrated CMOS parallel optical receiver front-end amplifier array

摘要: This paper presented a 12-channel parallel optical receiver front-end amplifier array design and realization in low cost 0.18 µm CMOS technology. Each channel incorporated transimpedance limiting amplifier. To meet the challenge for of high gain at date rate up to 10 Gb/s, an optimized circuit topology was proposed some bandwidth extension technologies were adopted, including regulated cascode, shunt peaking, active negative feedback. Against power consumption, crosstalk noise, corresponding solutions such as applying isolation structure array, optimization noise parameters Gb/s applications. The on-wafer measurements revealed that this chip’s operation speed reached per channel, 120 with operation. Consuming DC 853 mW from 1.8 V supply voltage, chip exhibits conversion 92.6 dBΩ, −3 dB 8 GHz, output swing input sensitivity bit-error 10−12 are 310 mV mVpp, respectively. size is 1142 µm×3816 testing pads.