Chip multi-processor scalability for single-threaded applications

摘要: The exponential increase in uniprocessor performance has begun to slow. Designers have been unable scale while managing thermal, power, and electrical effects. Furthermore, design complexity limits the size of monolithic processors that can be designed keeping costs reasonable. Industry responded by moving toward chip multi-processor architectures (CMP). These are composed from replicated utilizing die area afforded newer processes. While this approach mitigates issues with complexity, effects, it does nothing directly improve contemporary or future single-threaded applications.This paper examines scalability potential for exploiting parallelism applications on these CMP platforms. explores total available unmodified sequential then viability machines. Using results analysis, forecasts CMPs, using "intrinsic" a program, sustain improvement users come expect new only 6-8 years provided many successful parallelization efforts emerge. Given outlook, advocates exploring methodologies which achieve beyond limit programs.