Comparative evaluation of latency reducing and tolerating techniques

摘要: Techniques that can cope with the large latency of memory accesses are essential for achieving high processor utilization in large-scale shared-memory multiprocessors. In this paper, we consider four architectural techniques address problem: (i) hardware coherent caches, (ii) relaxed consistency, (iii) softwareconuolled prefetching, and (iv) multiple-context suppon. We some studies benefits individual have been done, no Study evaluates all within a consistent framework. This paper attempts to remedy by providing comprehensive evaluation techniques, both individually combinations, using set assumptions. The results obtained detailed simulations multiprocessor. Our show caches consistency UNformly improve performance. improvements due prefetching multiple contexts sizeable, but much more applicationdependent. Combinations various generally amin better performance than each one on its own. Overall, suitahle combinations be improved 4 7 dmes