作者: 良則 水谷 , 博章 石川 , Hiroaki Ishikawa , Yoshinori Mizutani , Masahito Sato
DOI:
关键词: Clock gating 、 Underclocking 、 Electronic engineering 、 Electrical engineering 、 CPU core voltage 、 Engineering 、 Digital clock manager 、 Clock rate 、 CPU multiplier 、 Clock domain crossing 、 Overclocking
摘要: PROBLEM TO BE SOLVED: To reduce the power consumption of equipment, to capacity supply part an use a small sized parts in current for source component by controlling frequency clock based on whether peripheral device is operated or not. SOLUTION: A CPU control block 5 inside system controller 4 always monitors operation request signals from devices 1 and 2. First all, when there no 2, corresponding signal 13, sets at ordinary state divider 6. Next, while operated, issues device-1 9. When this received, 1/4 COPYRIGHT: (C)1998,JPO