The Performance Potential of an Integrated Network Interface

摘要: High-bandwidth TCP/IP networking is a core component of current and future computer systems. Though central to computing today, the vast majority end-host research focuses on paradigm network interface being merely peripheral device. Most optimizations focus solely software changes or moving some computation from primary CPU off-chip controller (NIC). We present an alternative approach for achieving high performance networking. Rather than increasing complexity NIC, we directly integrate conventional NIC die. To evaluate this approach, have developed simulation environment specifically targeted networked It simulates server client systems along with in single process. Fullsystem captures execution both application OS code. Our model includes detailed out-of-order CPU, event-driven memory hierarchy, Ethernet Using simulator, find that tighter integration can provide benefits throughput latency. also see interaction on-chip hierarchy has greater impact raw improvements bandwidth latency come integration.