Mcml retention flip-flop/latch for low power applications
作者： Kuang-Kai Yen , Chewn-Pu Jou , Tsung-Hsiung Lee , Shi-Hung Wang , Fu-Lung Hsueh
DOI:
关键词: Electronic circuit 、 Power (physics) 、 Computer hardware 、 Power consumption 、 Engineering 、 Voltage 、 Flip-flop 、 Clock tree
摘要: The present disclosure relates to a device and method reduce the dynamic/static power consumption of an MCML logic device. In order retain register contents during off mode, retention latch flip-flop are disclosed. Retention Latch circuits in architecture used critical wherein combination including clock buffers on tree paths powered consumption. comprises master slave latch, switch is added mode. includes pull-down that remain active enable data at proper voltage level Other devices methods also
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