作者: George F. Riley
关键词: Network topology 、 Real-time computing 、 Topology (electrical circuits) 、 Scale (ratio) 、 Emphasis (telecommunications) 、 Network packet 、 Reduction (complexity) 、 Network simulation 、 Computer science
摘要: When designing a network simulation environment intended specifically for modeling large-scale topologies, number of issues must be addressed by the simulator designer. Memory requirements engines can grow quadratically with size simulated topology and easily exceed available memory on modern workstations. The outstanding events grows linearly packets in flight being modeled, lead to performance bottlenecks when managing sorted event list millions events. Tracking results using packet-level log file result excessive usage disk space. We discuss design Georgia Tech Network Simulator (GTNetS) emphasis how GTNetS addresses these issues. give from experiments showing reduction as our decisions.