作者: Jochen Jess , Chandramouli Visweswariah
DOI:
关键词: Static timing analysis 、 Macro 、 Integrated circuit 、 Statistical static timing analysis 、 Statistical model 、 Statistical timing 、 Probability distribution 、 Delay calculation 、 Electronic engineering 、 Computer science
摘要: A comprehensive methodology for statistical modeling and timing of integrated circuits circuit macros is disclosed with a means efficiently computing the sensitivities coefficients gate delay models to sources variation. These are used determine probability distribution slew each wire, as well correlations between these delays slews. Finally, in an inventive static analysis method predict performance or macro.