Asymptotically zero energy computing using split-level charge recovery logic
作者： Saed G. Younis , Frederic R. Morgenthaler
DOI:
关键词: Multiplier (economics) 、 Electrical engineering 、 Logic family 、 CMOS 、 Logic gate 、 Computation 、 Engineering 、 Pass transistor logic 、 Electronic circuit 、 Electronic engineering 、 Energy consumption
摘要: The dynamic dissipation of CMOS circuits is becoming a major concern for designers personal information systems and large computers. Here, we present new logic families, including Split-Level Charge Recovery Logic (SCRL), within which the transfer charge between nodes occurs quasistatically, thus having power consumption that drops quadratically with operating frequency as opposed to linear drop conventional CMOS. technique in these families rely on explicitly reversible pipelined gates provide necessary needed recover most energy used computation. We report results testing first fully quasistatic 8x8 multiplier chip (SCRL-1).
harvard.edu参考文章(0)