Design-for-Testability Techniques for Arithmetic Circuits
作者： Bo-Yuan Ye , Po-Yu Yeh , Sy-Yen Kuo , Ing-Yi Chen
DOI: 10.1109/CAS-ICTD.2009.4960806
关键词: Arithmetic 、 Finite impulse response 、 Mathematics 、 Saturation arithmetic 、 Subtractor 、 Bijection 、 Design for testing 、 Algorithm 、 Multiplier (Fourier analysis) 、 Electronic circuit 、 Adder
摘要: In this paper, a novel test technique is proposed to achieve C-testable DFT designs for arithmetic circuits. Base on famous iterative-logic-array (ILA) scheme, basic bijective cells (one-to-one mapped I/O function) adder, subtracter, adder-subtractor and multiplier are proposed. particular, these always any word-length n. Thus the can be easily connected together various circuits such as accumulator, FIR (Finite Impulse Response) filter, regarded ILAs. The solutions reused or cascaded with similar structure Besides, all tested saving lots of pins BIST (Build-in Self Test) area.
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