作者: Nathan Chelstrom , Shoji Sawamura , Mack Riley
DOI:
关键词: Synchronous circuit 、 Electronic engineering 、 Timing failure 、 Computer science 、 Clock gating 、 Clock skew 、 Signal 、 Control theory 、 Self-clocking signal 、 Clock domain crossing 、 Clock signal
摘要: The present invention provides a data processing system, method, and computer program product for stopping at least two clock signals that oscillate different frequencies restarting the their correct phase. A RUNN counter stops signals. faster signal restarts phase status circuit determines where slower stopped produces signal. second utilizes to start Therefore, insures are restarted In another embodiment, enables desired