作者: Tei-Wei Kuo , Yung-Chun Li , Yuan-Hao Chang , Hsiang-Pang Li , Cheng-Yuan Wang
DOI:
关键词: Group (periodic table) 、 Computer science 、 Non-volatile memory 、 Computer hardware 、 NAND gate 、 Reduction (complexity) 、 Parallel computing 、 Block (data storage)
摘要: Technology is described that supports reduced program disturb of nonvolatile memory. A three/two dimensional NAND array includes a plurality pages, which are divided into page groups. Access allowed to memory cells within first group groups in an erase block the three array, while access minimized second array. Pages same physically nonadjacent with each other