摘要: In FPGAs, the internal connections in a cluster of lookup tables (LUTs) are often fully-connected like full crossbar. Such high degree connectivity makes routing easier, but has significant area overhead. This paper explores use sparse crossbars as switch matrix inside clusters between inputs and LUT inputs. We have reduced densities these matrices by 50% or more saved from 10 to 18% with no degradation critical-path delay. To compensate for loss routability, increased compute time spare required. Further investigation may yield modest delay reductions.
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sci-hub.se 参考文章(12)
Alexander Marquardt, Vaughn Betz, Jonathan Rose, Architecture and CAD for Deep-Submicron FPGAS ,(1999)
W. C. Elmore, The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers Journal of Applied Physics. ,vol. 19, pp. 55- 63 ,(1948) , 10.1063/1.1697872
Mike Sheng, Jonathan Rose, Mixing buffers and pass transistors in FPGA routing architectures field programmable gate arrays. pp. 75- 84 ,(2001) , 10.1145/360276.360302
Elias Ahmed, Jonathan Rose, The effect of LUT and cluster size on deep-submicron FPGA performance and density field programmable gate arrays. pp. 3- 12 ,(2000) , 10.1145/329166.329171
Alexander Marquardt, Vaughn Betz, Jonathan Rose, Timing-driven placement for FPGAs field programmable gate arrays. pp. 203- 213 ,(2000) , 10.1145/329166.329208
Guy Lemieux, Paul Leventis, David Lewis, Generating highly-routable sparse crossbars for PLDs field programmable gate arrays. pp. 155- 164 ,(2000) , 10.1145/329166.329199
J. Cong, Yuzheng Ding, FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. ,vol. 13, pp. 1- 12 ,(1994) , 10.1109/43.273754
Alexander (Sandy) Marquardt, Vaughn Betz, Jonathan Rose, Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays - FPGA '99. pp. 37- 46 ,(1999) , 10.1145/296399.296426
Elias Ahmed, THE EFFECT OF LOGIC BLOCK GRANULARITY ON DEEP-SUBMICRON FPGA PERFORMANCE AND DENSITY ,(2001)
Vaughn Betz, Jonathan Rose, VPR: A new packing, placement and routing tool for FPGA research field programmable logic and applications. pp. 213- 222 ,(1997) , 10.1007/3-540-63465-7_226