Overlay test wafer
作者： Christopher P. Ausschnitt
DOI:
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摘要: The present invention is directed to an improved test wafer for testing the overlay alignment of a second level pattern over first lithographic equipment used in making microcircuits, which includes four conductors with circuitry provided each conductor measuring conductance thereof, being constructed and arranged so that relative conductor, third fourth indicative offset said respect pattern. In another form additional are thereof direction orthogonal group conductors.
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