Program Slicing of Hardware Description Languages

摘要: Hardware description languages (HDLs) are used today to describe circuits at all levels. In large HDL programs, there is a need for source code reduction techniques address myriad of problems in formal verification, design, simulation, and testing. Program slicing static program analysis technique that allows an analyst automatically extract portions programs relevant the aspects being analyzed. We extend HDLs, thus allowing automatic allow user focus on portions. have implemented VHDL tool composed general inter-procedural slicer front-end captures execution semantics. This paper provides overview slicing, discussion how slice resulting tool, brief some applications experimental results.