Apparatus method and system for 64 bit peripheral component interconnect bus using accelerated graphics port logic circuits

摘要: A multiple use core logic chip set is provided in a computer system that may be configured either as bridge between an accelerated graphics port ("AGP") bus and host memory buses, 64 bit additional peripheral component interconnect ("PCI") the or primary PCI bus. The function of determined at time manufacture field whether AGP to implemented. has arbiter having Request ("REQ") Grant ("GNT") signal lines for each device utilized on Selection type (AGP PCI) made by hardware input, software during configuration power self test ("POST"). Software also upon detection connected common