Destination address detection apparatus for hardware packet router

摘要: An improved destination address detection apparatus for a hardware packet router capable of detecting the to which data is transmitted, not using central processing unit, includes serial/parallel converter converting serial inputted thereto into parallel data; buffer storing outputted from therein and outputting in first-in-first-out method; an detector destination, buffer; "n" number buffers, are activated accordance with detected by detector, method, wherein said latches, connected series, sequentially shifting output signals outputting; decoding latch signal generating chip enable when stored, selectively enabling buffers.