Semi-iterative analogue turbo decoding : an application to DVB-RCS-like codes

摘要: Over the past decade, telecommunication systems have dramatically grown providing services which require ever more data rate with mobility. To sustain this growth, enhanced and new techniques were implemented in optimised digital circuits. A novel approach could be soon necessary for some of these techniques, due to limitations their hardware implementations. Error correction is one them. It allows reduce energy used send information, but, when on a chip, it bottleneck terms throughput of, paradoxically, power consumption. The analogue iterative decoding solve problem. This technique, promising high performance, requires architectures codes adapted constraints processing challenge circuits field industrial applications. architecture turbo algorithm, offering good compromise between onchip area rate, are proposed thesis. They pave way integrating flexible high-speed decoders dealing different frame lengths ranging from few dozen thousand bits. algorithm applied DVB-RCS-like code. component 8-state decoder was designed 0. 25µm BiCMOS process. Dealing frames made up 24 double-binary symbols, is, date, most complex designed. Implemented circuit successfully tested at 100Mbit/s while consuming 414mW 2. 8V core supply. shown provide bit error as close 3dB