摘要: This paper presents a simulation-based performance evaluation of shared-memory multiprocessor using the Scalable Coherent Interface (IEEE 1596). The machines are assembled with one to 16 processors connected in ring. multiprocessor's memory hierarchy consists split primary caches, coherent secondary caches and memory. For workload two parallel loops three thread-based programs, cache latency has strongest impact on performance. programs high miss ratios, 16-node rings exhibit network congestion whereas 4and 8-node perform better. With these same doubling processor speed yields between 20 70% gains higher smaller rings.
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