A display port link between a processor and a display device
作者： Colin Whitby-Strevens , Sreeraman Anantharaman
DOI:
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摘要: Video data (58) and auxiliary (60) may be sent between a processor (18) display device (12) via single cable (62) using link aggregator (28). As such, the receive first parallel signal that include video second from processor. The (28) then send as an aggregated to device. Upon receiving (54) at device, de-aggregate into (60). timing controller (56) of such
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