Biasing and sizing of the MOS transistor in weak inversion for low voltage applications

摘要: Methods and circuits are disclosed for low voltage (1.5 Volt below) CMOS circuits, offering good transconductance current driving capabilities. These goals achieved by biasing transistors in the weak inversion region, utilizing multiple unit-sized with a fixed gate width to length ratio, maintaining uniform threshold of each transistor. The required transistor size is obtained parallel connection several transistors, such that `n` unit sized carry units. methods eliminate deviation output mirrors caused mismatch. Disclosed mirror two typical amplifiers as examples design.