Device for generating clock signals for asymmetric comparison of phase errors
作者： Eric Colinet , Anton Korniienko , Dimitri Galayko
DOI:
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摘要: The invention relates to a device for generating clock signals, comprising phase locked loop (100) including: - controlled oscillator (101) capable of outputting signal, plurality comparators (102.1-102.4) comparing signal output by the with phases applied input loop, means (110) weighted summing signals from such that one or more weighting coefficients said has an absolute value which overrides values other filtering (112) sum comparators, are control oscillator.
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lens.org 参考文章(20)
Hirokazu Goto, Interstation synchronization apparatus ,(1968)
John Nguyen, Gill Andrews Pratt, Synchronization of hardware oscillators in a mesh-connected parallel processor ,(1992)
P.M. Levine, G.W. Roberts, A high-resolution flash time-to-digital converter and calibration scheme international test conference. pp. 1148- 1157 ,(2004) , 10.1109/TEST.2004.1387389
T. Saito, Application of Phase-Locked Oscillator for PCM Network Synchronization IEEE Transactions on Communications. ,vol. 30, pp. 2344- 2354 ,(1982) , 10.1109/TCOM.1982.1095409
A. Korniienko, E. Colinet, G. Scorletti, E. Blanco, H ∞ loop shaping control for distributed PLL network conference on ph.d. research in microelectronics and electronics. pp. 336- 339 ,(2009) , 10.1109/RME.2009.5201324
JosÉ A. Tierno, Alexander V. Rylyakov, Daniel J. Friedman, A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI IEEE Journal of Solid-state Circuits. ,vol. 43, pp. 42- 51 ,(2008) , 10.1109/JSSC.2007.910966
V. Gutnik, A.P. Chandrakasan, Active GHz clock network using distributed PLLs international solid-state circuits conference. ,vol. 35, pp. 1553- 1560 ,(2000) , 10.1109/4.881199
G.A. Pratt, J. Nguyen, Distributed synchronous clocking IEEE Transactions on Parallel and Distributed Systems. ,vol. 6, pp. 314- 328 ,(1995) , 10.1109/71.372779