Wave-Pipelined eSFQ Circuits

摘要: We have designed and tested energy-efficient single flux quantum (eSFQ) circuits suitable for wave-pipelined architectures. The high energy-efficiency of eSFQ combined with the sequential nature SFQ logic makes especially variants highly-pipelined such as modern arithmetic units (ALUs), without penalty to clock speeds available RSFQ logic. In previous work, we demonstrated working in form shift registers, deserializers, counters. Here expand on this work by introducing a means moving data through need buffering at every step, resembling architecture characterizing many large circuits. Specifically, present pipeline-friendly JTL, confluence buffer, half adder, comprising core components adder also show how an full naturally lends itself utilization computation pipeline. report experimental demonstration manufactured Hypres's 4.5 kA/cm 2 process.