Sub-1-V design techniques for high-linearity multistage/pipelined analog-to-digital converters
作者： Dong-Young Chang , Gil-Cho Ahn , Un-Ku Moon
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摘要: The design of an ultra-low-voltage multistage (two-stage algorithmic) analog-to-digital converter (ADC) employing the opamp-reset switching technique is described. A highly linear input sampling circuit accommodates truly low-voltage from external signal source. radix-based digital calibration used to compensate for component mismatches and reduced opamp gain under low supply voltage. scheme based on a half-reference multiplying digital-to-analog structure, where error sources seen by both reference paths are made identical given stage. prototype ADC was fabricated in 0.18-/spl mu/m CMOS process. integrated dissipates 9 mW at 0.9-V with range 0.9 V/sub p-p/ differential. improves signal-to-noise-plus-distortion ratio 40 55 dB spurious-free dynamic 47 75 dB.
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