Method and apparatus for embedding operand synthesizing sequences in randomly generated tests

摘要: In a conventional random test generator, instructions are generated, pushed onto queue, and then popped off of the queue in generation order. The methods apparatus disclosed herein provide means associating delay with each generated instruction. Instructions therefore response to their associated delay, rather than Since instruction synthesizing sequence (e.g., load sequence) is randomly may be numerous times, yet never appear as same device under test. Furthermore, no register reserved for special purpose. As result, disadvantages generating techniques overcome.