Architecture for high sampling rate, high resolution analog-to-digital converter system

摘要: A high resolution analog-to-digital (A/D) converter (14) and a pipelined A/D are used in single system so that unknown offset gain errors of the pipe-lined determined corrected. Each stage includes flash (16), corresponding digital-to-analog (D/A) (18), differential amplifier (20) that, each output voltage D/A is subtracted from sample analog input voltage, to constitute signal for next stage. The addresses digital words memory (22) which, when summed by an adder chain (24), system. signals also supplied stages shift register (28 or 28') which accumulates address bits. comparator finite state machine (26) receives bits iteratively compares corrects addressed converters improve