Design of an efficient RF-DC voltage multiplier for RF Energy Harvesting Applications

摘要: In this paper, a RF-DC voltage multiplier is presented to efficiently convert RF signals DC voltages. The proposed circuit uses an internal threshold cancellation (IVC) scheme with auxiliary block reduce the of forward-biased transistors and minimizes reverse leakage current reverse-biased by dynamically controlling gate-source in main rectification chain. designed 0.18 um CMOS technology. A three-stage results maximum power conversion efficiency (PCE) 49.1% at input level 0 dBm frequency 900 MHz. produces output 4.94 V 50 KΩ load.