Architectural Support for Software Transactional Memory

摘要: Transactional memory provides a concurrency control mechanism that avoids many of the pitfalls lock-based synchronization. Researchers have proposed several different implementations transactional memory, broadly classified into software (STM) and hardware (HTM). Both approaches their pros cons: STMs provide rich flexible semantics on stock processors but incur significant overheads. HTMs, other hand, high performance implement restricted or add complexity. This paper is first to propose architectural support for accelerating transactions executed entirely in software. We instruction set architecture (ISA) extensions novel mechanisms improve STM performance. adapt high-performance algorithm supporting our ISA (called accelerated HASTM). HASTM accelerates fully virtualized nested transactions, supports language integration, both object-based cache-line based conflict detection. implemented an accurate multi-core IA32 simulator. Our simulation results show (1) single-thread comparable conventional HTM implementation; (2) scaling (3) resilient spurious aborts can scale better than setting. Thus, flexibility STM, while giving HTM.