Speculative instructions exection in VLIW processors
作者： Andre Pauporte , Francois Jacob
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摘要: The object of the present invention is to improve execution instructions using speculative operations in Superscalar or Very Long Instruction Word (VLIW) processors having multiple Arithmetic Logic Units (ALUs). More particularly, relates a system and method for standard registers as shadow registers. addresses all are translated Relocation Table (RT) array. used another time Speculative Registers (SRT) At branch completion time, that have previously been executed correctly predicted, updated with content. For incorrectly remains unchanged. performs same function state art hardware while limited number read/write ports register
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