Reconstructing hardware transactional memory for workload optimized systems

摘要: Workload optimized systems consisting of large number general and special purpose cores, with a support for shared memory programming, are slowly becoming prevalent. One the major impediments effective parallel programming on these is lock-based synchronization. An alternate synchronization solution called Transactional Memory (TM) currently being explored.We observe that most TM design proposals in literature catered to match constrains computing platforms. Given fact workload utilize wider hardware spaces on-chip parallelism, we argue Hardware (HTM) can be suitable implementation choice systems. We re-evaluate criteria satisfied by HTM identify possible scope relaxations context Based relaxed criteria, demonstrate building variants, such that, each variant caters specific requirement. carry out experiments bring about trade-off between variants. Overall, show how knowledge extremely useful make appropriate choices HTM.