A Parallel Hardware Architecture For Quantum Annealing Algorithm Acceleration

摘要: Quantum Annealing (QA) is an emerging technique, derived from Simulated Annealing, providing metaheuristics for multivariable optimisation problems. Studies have shown that it can be applied to solve NP-hard problems with faster convergence and better quality of result than other traditional heuristics, potential applications in a variety fields, transport logistics circuit synthesis optimisation. In this paper, we present hardware architecture implementing QA-based solver the Multidimensional Knapsack Problem, designed improve performance algorithm by exploiting parallelised computation. We synthesised using as target Altera FPGA board simulated execution solving set benchmarks available literature. Simulation results show proposed implementation about 100 times single-thread general-purpose CPU without impact on accuracy solution.