Line-locked clock signal generation system
作者： Toshio Kaneuchi , Kazuo Fukazawa
DOI:
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摘要: A television receiver includes a phase-locked loop (PLL) which generates clock signal having frequency of N times the line and being to horizontal synchronizing signal. The produced by this PLL has tends jitter between N+1 N-1 frequency. To compensate for jittering in signal, phase alignment circuitry is coupled align drive on occurrence each pulse. also delay element delays applied comparator PLL. This effectively advances line-locked with respect sync processing imparted generation
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