Highly stable threshold voltage in GaN nanowire FETs: The advantages of p-GaN channel/Al2O3 gate insulator

摘要: We present an extensive investigation of the charge-trapping processes in vertical GaN nanowire FETs with a gate-all-around structure. Two sets devices were investigated: Gen1 samples have unipolar (n-type) epitaxy, whereas Gen2 p-doped channel and n-p-n gate stack. From experimental results, we demonstrate superior performance transistor structure p-GaN channel/Al2O3 insulator terms dc performance. In addition, that highly stable threshold voltage, thus representing ideal for power electronic applications. Insight into trapping two generations was obtained by modeling voltage variations via differential rate equations.