VLSI implementation of a digital neural network with reward-penalty learning

摘要: The use of networks logical processing elements to effect pattern matching and recognition has been the subject much research since birth digital microelectronic systems. In 1959, Bledsoe Browning (59) proposed N-Tuple method recognition. technique offered a relatively low-cost approximation Bayesian classification formed basis for many studies in sixties (see instance, Steck 62, Ullmann 69). Later, Aleksander colleagues exploited potential RAM technology develop hardware realisations which allowed real time learning (the WIS ARD system, 84).