SPR

摘要: In this paper we present SPR, a new architecture-adaptive mapping tool for use with Coarse-Grained Reconfigurable Architectures (CGRAs). It combines VLIW style scheduler and FPGA placement pipelined routing algorithms novel mechanisms integrating adapting the to CGRAs. We introduce latency padding technique that provides feedback from placer meet constraints of fixed frequency device configurable interconnect. Using dynamic clustering method during placement, achieved 1.3x improvement in throughput mapped designs. Finally, an enhancement PathFinder algorithm targeting architectures mix dynamically multiplexed statically interconnects. The enhanced is able successfully share configured interconnect time-multiplexed way, achieving average channel width reduction .5x compared non-shared static