作者: William Stonecypher , Jared Zerbe , Mark Horowitz , Dennis Kim
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摘要: A circuit, apparatus and method obtains system margin at the receive circuit using phase shifted data sampling clocks while allowing CDR to remain synchronized with incoming stream in embodiments. In an embodiment, a includes first second samplers sample signal output edge information response clock signal. detector generates information. adjustment during synchronization mode. The increments of waveform capture