作者: Koichi Kuroiwa , Kenji Shirasawa , Hiromasa Takahashi , Hideyuki Iino , Hiroyuki Fujiyama
DOI:
关键词:
摘要: A memory accessing device is connected to a central processing unit and via common bus. The accesses the independently of unit. includes an address generating for address, control outputting generated bus, controlling suspend or terminate access controlled in pipeline mode when internally externally issues request suspension termination mode. terminates suspends it receives access.