Information processing apparatus, multithread matrix operation method, and multithread matrix operation program

作者: Takeshige Kazuaki

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摘要: An information processing apparatus includes a memory; and processor. The processor is configured to execute partitioning predetermined matrix whose values of elements are be generated by operation, into number first submatrices dimension in at least one row direction column multiple block size corresponding registers used for the second that different from submatrices; assigning operation generate each submatrices, threads.

参考文章(30)
Srinidhi Kestur, Eric Chung, John D. Davis, Universal fpga/asic matrix-vector multiplication architecture ,(2012)
Cezary Dendek, Pawel Cichosz, Michal Draminski, Krzysztof Skowronski, Miezyslaw Klopotek, Distributed processing of data records ,(2014)
Natalya Kuznetsova, Oleg Diyankov, Sergey Koshelev, Vladislav Pravilnikov, Serguei Maliassov, Method for solving reservoir simulation matrix equation using parallel multi-level incomplete factorizations ,(2009)
Gregorio Quintana-Ortí, Enrique S. Quintana-Ortí, Robert A. Van De Geijn, Field G. Van Zee, Ernie Chan, Programming matrix algorithms-by-blocks for thread-level parallelism ACM Transactions on Mathematical Software. ,vol. 36, pp. 1- 26 ,(2009) , 10.1145/1527286.1527288
Xing Liu, Mikhail Smelyanskiy, Edmond Chow, Pradeep Dubey, Efficient sparse matrix-vector multiplication on x86-based many-core processors Proceedings of the 27th international ACM conference on International conference on supercomputing - ICS '13. pp. 273- 282 ,(2013) , 10.1145/2464996.2465013
Hyuk-Jae Lee, James P. Robertson, José A. B. Fortes, Generalized Cannon's algorithm for parallel matrix multiplication international conference on supercomputing. pp. 44- 51 ,(1997) , 10.1145/263580.263591