Temperature and Process Variations Aware Dual Threshold Voltage Footed Domino Circuits Leakage Management

摘要: Considering the effect of temperature and process variations, inputs clock signals combination sleep state dependent leakage current characteristics is analyzed optimal examined in sub-65nm dual threshold voltage (Vt) footed domino circuits. HSPICE simulations based on 65nm 45nm BSIM4 models show that proposed CLIL (the signal are all low) to reduce high fan-in circuits at almost room temperature, as compared conventional CHIL CHIH high). Further, influence variations Vt evaluated. At last, variation aware new low setup guidelines provided.