Switchable DAC with current surge protection

摘要: In a CMOS DAC having plurality of stages control circuit for selectively switching said between sleep mode and normal operating with little, if any, surge current resulting therefrom. the there is provided transistors responsive to signals applying reverse biasing potential reference voltage transistor digital input in each at rate such that change less than predetermined magnitude, e.g. 5 ma/nsec. when switched its means first forward bias thereafter changing applied removing from mode.