An integrated high resolution CMOS timing generator based on an array of delay locked loops
作者： J. Christiansen
DOI: 10.1109/4.508208
关键词:
摘要: This paper describes the architecture and performance of a new high resolution timing generator used as building block for time-to-digital converters (TDC) clock alignment functions. The is implemented an array delay locked loops. enables with subgate to be in standard digital CMOS process. TDC function by storing state signals asynchronous pipeline buffer when hit signal asserted. obtained selecting one output clock. proposed has been mapped into 1.0 /spl mu/m process r.m.s. error time taps 48 ps measured bin size 0.15 ns. Used device, 76 obtained, A short overview basic principles major architectures given compare merits scheme other alternatives.
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