Self-reconfigurable architectures for HEVC Forward and Inverse Transform

摘要: This work introduces a run-time reconfigurable system for HEVC Forward and Inverse Transforms that can adapt to time-varying requirements on resources, throughput, video coding efficiency. Three scalable designs are presented: fully parallel, semi iterative. Performance scalability is achieved by combining folded/unfolded 1D Transform architectures one/two transposition buffers. Resource usage optimized utilizing both the recursive evenodd decomposition distributed arithmetic techniques. The architecture design supports sequences in 8K Ultra High Definition format (76804320) with up 70 frames per second when using 6464 Coding Tree Blocks variable transform sizes. self-reconfigurable embedded implemented tested Xilinx Zynq-7000 All-Programmable System-on-Chip (SoC). Results presented terms of performance (frames second), resource utilization, hardware adaptation variety parameters, resolutions, self-reconfigurability scenarios. illustrates advantages reconfiguration technology PSoCs or FPGAs compression. Self-reconfigurable trade-off resources performance.The parameterized code allows large space exploration.A different efficiency requirement trigger reconfiguration.A case made encoders decoders.