Jointly Designed Architecture-Aware LDPC Convolutional Codes and High-Throughput Parallel Encoders/Decoders

摘要: A novel design approach is proposed for low-density parity-check convolutional codes (LDPC-CCs), that jointly optimizes the code, encoder and decoder to achieve high-throughput parallel encoding decoding. series of implementation-oriented constraints are applied construct architecture-aware (AA) by introducing algebraic structures into matrix. The resulting AA have bit error rate performance comparable other published LDPC-CCs. Given these LDPC-CCs, new architectures a LDPC-CC with built-in termination an in node dimension as well pipelined iteration dimension. ASIC synthesis results 90-nm CMOS process show decoding processor 2.0-Gbps throughputs at 250-MHz clock frequencies within silicon areas 0.1 mm2 1 respectively.