Methods and apparatus for providing a user oriented microprocessor test interface for a complex, single chip, general purpose central processing unit

摘要: Methods and apparatus are disclosed that facilitate the testing development of computer systems include at least one single chip microprocessor. In particular, a parallel test interface is described allows an external unit to (1) directly load instructions into microprocessor under utilizing existing bus structure system; (2) step processor through preselected instruction sequences; (3) monitor states in both processor's normal execution modes; (4) halt resume processing. According invention, comprises plurality dedicated CPU status output pins control input pins, used by combination with system provide desired facility for The preferred embodiment invention realized RISC environment where lengths fixed has cycle time. Such facilitates direct insertion tester decoding, without having queue or pass complicated intervening hardware logic.