Architecture design of resistor/FET-logic demultiplexer for hybrid CMOS/nanodevice circuit interconnect.

摘要: Hybrid nanoelectronics consisting of nanodevice crossbars on top CMOS backplane circuits is emerging as one viable option to sustain Moore's law after the scaling limit reached. One main design challenge in such hybrid interface between highly dense nanowires and relatively coarse microwires domain. Such an can be realized through a logic circuit called demultiplexer (demux). In this context, all prior work demux uses single type device, resistor, diode or field effect transistor (FET), realize demultiplexing function. However, different types devices have their own advantages disadvantages terms functionality, manufacturability, speed power consumption. This makes none them provide satisfactory solution. To tackle challenge, proposes combine resistor with FET implement demux, leading resistor/FET-logic demux. architecture make these two complement each other well improve overall effectiveness. Furthermore, due inevitable fabrication process variations at nanoscale, effects conductance threshold voltage variability are analyzed evaluated based computer simulations. The simulation results requirement ensure high reliability, promise improved addressability variance tolerance.