A 2-bit 1Gsps ADC Array with 32:1 Serializer in 45nm CMOS SOI Technology
作者： Geng Tian
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摘要: In this thesis, a SoC (system on chip) solution is proposed for the IF (intermediate frequency) band signal processing and transmission of radiometer system. This highly integrated low-power designed systems where low ADC resolution ( 10Gbps) operation (< 10mW/channel) strongly desired. The presented includes an array 2-bit ADCs with duty cycle controlled AGC (automatic gain control) function 32:1 serializer. included in front end order to cope wide range input power (-10dBm ~ -20dBm). loop by digitized output error 2%. A current steering 5-level tree architecture serializer achieve high serializing factor operation.The circuit using 45nm SOI CMOS technology. It capable digitizing signals 5.4mW/channel transmitting at 32Gbps. has reflection (S22) less than -10dB from DC 32GHz 400mV differential swing. consumes 50mW (3.2mW/channel), 2.2mW/channel.
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