Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM
作者： Bernard J New , Robert Anders Johnson , Ralph Wittig , Sundarajarao Mohan , None
DOI:
关键词:
摘要: A field programmable gate array (FPGA) which includes first and second arrays of configurable logic blocks, configuration cache memories coupled to the respectively. The memory can either store values for reconfiguring or operate as a RAM. Similarly, are independently controlled, such that partial reconfiguration FPGA be accomplished. In addition, (rather than second) thereby providing second-level memory.
google.co.in 参考文章(9)
Philip M. Freidin, Virtual high density programmable integrated circuit having addressable shared memory cells ,(1996)
Ian Eslick, Andre DeHon, Edward Tau, Michael Bolotski, Thomas F. Knight, Derrick Chen, Jeremy Brown, Dynamically programmable gate array with multiple contexts ,(1995)
Thomas A. Kean, Embedded memory for field programmable gate array ,(1996)
Web Chang, Application specific field programmable gate array ,(1996)
Thomas A. Kean, Programmable switch for FPGA input/output signals ,(2000)
Richard A. Carberry, Stephen M. Trimberger, Jennifer Wong, Robert A. Johnson, Configuration modes for a time multiplexed programmable logic device ,(1995)
Ross H. Freeman, Configurable electrical circuit having configurable logic elements and configurable interconnects ,(1988)