2-D Differential Folded Vertical Hall Device Fabricated on a P-Type Substrate Using CMOS Technology

摘要: This paper investigates a two-dimensional (2-D) differential folded vertical Hall device (VHD) fabricated using standard 0.35 $\mu{\rm m}$ CMOS technology. To minimize the cross-coupling noise, proposed VHD is laterally to shorten effective conduction length, and ${\rm p}^{+}$ guard ring shortens length narrow conducting channel. The sensitive in-plane magnetic induction based on combinational effects between bulk magnetotransistor (BMT), magnetoresistor (VMR), (VMT); that BMT implemented with p-substrate enhance magnetosensitivity. measurement results show dominant mechanism in view of (VMR) (VMT). Additionally, VMT scales down range considerably whereas VMR enhances VHD. key factor increase nonlinearity error. Integrating or enables high measured voltage respect applied (B), but both are linear B by integrating VMT. operates small hysteresis, its sensitivity highest when bias current low.