VLSI Implementation of LDPC Codes

摘要: Coded modulation is a bandwidth-efficient scheme that integrates channel coding and into one single entity to improve performance with the same spectral efficiency compared uncoded modulation. Low-density parity-check (LDPC) codes are most powerful error correction (ECCs) approach Shannon limit, while having relatively low decoding complexity. Therefore, idea of combining LDPC has been widely considered. In this thesis we will consider as an Error Correcting Code study it’s BPSK system in AWGN environment different kind characteristics system. consists two parts Encoder Decoder. encoder encodes data sends it channel. The encoding depends on Parity matrix behavior which like Rate, Girth, Size Regularity. We according these find variation term SNR performance. decoder receives from decodes it. time iteration addition all parity check characteristics. also main objective implement FPGA. implementation done using Shift-Register based design reduce used decode information received message information. have Modified Sum Product (MSP) Algorithm decode, MSP some quantized values Look Up Table (LUT) approximation. Finally compare theoretical system’s FPGA implemented