Storage device and information processing system

作者: Toshiyuki Shinagawa-ku Nishihara , Yoshio Shinagawa-ku Sakai

DOI:

关键词:

摘要: A storage device able to make a redundant write operation of unselected data unnecessary and optimize an arrangement pages state having high efficiency for rewriting, wherein the has first memory unit, second unit different access speed from memory, control circuit, circuit function timely moving stored in two ways between speeds reading or rewriting.

参考文章(24)
Tsuyoshi Motokurumada, Aiichiro Inoue, Masaki Ukai, Yuji Shirahige, Pre-fetch control device, data processing apparatus and pre-fetch control method ,(2003)
Kenneth Mark Wilson, Robert B. Aglietti, Relocation table for use in memory management ,(2001)
Robert Royer, Richard Coulson, Brian Leete, Method and system to alter a cache policy ,(2003)
K. Inoue, T. Naka, N. Awaya, A. Sakiyama, Y. Wang, S.Q. Liu, N.J. Wu, A. Ignatiev, W.W. Zhuang, W. Pan, B.D. Ulrich, J.J. Lee, L. Stecker, A. Burmaster, D.R. Evans, S.T. Hsu, M. Tajiri, A. Shimaoka, Novel colossal magnetoresistive thin film nonvolatile resistance random access memory (RRAM) international electron devices meeting. pp. 193- 196 ,(2002) , 10.1109/IEDM.2002.1175811
R. Scheuerlein, W. Gallagher, S. Parkin, A. Lee, S. Ray, R. Robertazzi, W. Reohr, A 10 ns read and write non-volatile memory array using a magnetic tunnel junction and FET switch in each cell international solid-state circuits conference. pp. 128- 129 ,(2000) , 10.1109/ISSCC.2000.839717
Pascal Sainrat, Fatima-Zahra Elkhlifi, Daniel Litaize, Jean-Claude Salinier, Abdelaziz Mzoughi, Mustapha Lalam, Process for exchanging information in a multiprocessor system ,(2003)
Takashi Tsunehiro, Yosio Takaya, Kenichi Kaki, Hajime Yamagami, Manabu Saito, Takao Okubo, Masamichi Kishi, Yukihiro Seki, Takeshi Wada, Shigeru Kadowaki, Takeshi Suzuki, Tsunehiro Tobita, Kunihiro Katayama, Takashi Kikuchi, Ryuichi Hattori, Jun Kitahara, Takashi Totsuka, Flash memory control method and apparatus processing system therewith ,(2001)
H. Nakamura, K. Imamiya, T. Himeno, T. Yamamura, T. Ikehashi, K. Takeuchi, K. Kanda, K. Hosono, T. Futatsuyama, K. Kawai, R. Shirota, N. Arai, F. Arai, K. Hatakeyama, H. Hazama, M. Saito, H. Meguro, K. Conley, K. Quader, Jian Chen, A 125mm/sup 2/ 1Gb NAND flash memory with 10MB/s program throughput international solid-state circuits conference. ,vol. 2, pp. 82- 411 ,(2002) , 10.1109/ISSCC.2002.992123